• DESIGN AND VALIDATION OF LOW NOISE LOW POWER AND HIGH EFFICIENT THREE STAGE COMPARATOR USING 45NM CMOS TECHNOLOGY

Suresh Kumar

Abstract: As a crucial component of both digital and analogue engineering, CMOS comparators are starting to play an important role in the amplifier stage, which involves signal conversion. Because the accuracy, input offset, and resolution of analogue-to-digital converters [1] depend on the setup, their specifications are quite restricted. To improve the ADC's resolution, input noise reduction, speed restriction, offset characteristics, and overall performance, high-end it is critical to configure CMOS comparatorsStrong ARM latches are functional and have been used for some time. Because of its positive feedback nature, Strong ARM architecture offers a number of benefits, such as low static power consumption and the maximum comparability with low leakage currents. We must acknowledge that there are constraints. Leakage current limits the comparators' speed, which is the main issue with latch source current. The Strong ARM's input stage pairs are responsible for producing this leakage current. Half of the bias voltage is used to restrict current due to the common mode [2] stage across the input stage. A higher input voltage from the power source is required due to the increased number of transistors. The source leakage current is reduced using the two-stage comparator approach. Figure 1 shows that Miyahara's design is two-staged.